Image sensors implemented in complementary metal oxide semiconductor (CMOS) are known and widely used in many applications that were once dominated by CCD imagers. Owing to an increased demand of high resolution imagers in the market, there have been continuous efforts to scale down the pixel size of the CMOS imagers by adopting the smaller geometry process allowed by new advancements in the CMOS process. The typical CMOS active pixel sensor (APS) comprises a three transistor (3-T) pixel or a four transistor (4-T) pixel. The detecting area of the pixel is typically smaller than the physical pixel dimension due to the areas of the transistors which are readout circuit elements, not detecting elements. The percentage ratio of the photodetector area to the pixel area is referred to as the optical fill factor. A typical fill factor of a small pixel APS without using a microlens is around 30%. Despite the numerous advantages of the CMOS APS over CCD's, its performance is significantly limited by the low fill factor.
Passive pixels, however, have the advantage of having a higher fill factor because they comprises fewer non-detecting components.
Most CMOS imagers currently use microlens, which needs additional fabrication processing to enhance the fill factor by focusing the light beam on the photodetector. As pixel size shrinks beyond 2 um×2 um, however, enhancement of the fill factor by using the microlens becomes negligibly small. Consequently, the reduction in the pixel size results in reduction in the optical fill factor and low quantum efficiency (QE).
In addition to the fill factor issue, light needs to penetrate into multiple thick dielectric layers until it reaches down to the surface of the photodetector. At each interface between the layers, light is reflected due to the refractive index variations. Also light energy is lost during the transmission of these thick layers. This light transmission loss is proportional to the number of layers and thickness of the layers. The multiple dielectric layers are formed due to CMOS fabrication requirements. Typically, modern CMOS processes employ 5 to 6 metal layers for the image sensor fabrication. This leads to depositions of 5 um to 6 um thick dielectric layers because each dielectric layer plus metal layer is 1.0 um thick or so. Above the photodetector where no metal layers are present dielectric layers are filled in for the planarization of the each stack layer.
As a result, light energy loss due to transmission loss becomes significant. In addition, there is another severe problem due to the thick dielectric layers. When a pixel pitch is as small as 2.0 um or even smaller, the photodetector width would be 1 um or smaller. Then, the aspect ratio of the stack height to the size of the opening window of the metal layers above the photodetector is higher than 6. In this case, a light beam is easily blocked by the metal over-layers when the light is incident in angles other than perpendicular to the imaging plane. If a microlens is employed, the aspect ratio becomes even higher and results in a worse light shadow effect. This light shadowing becomes worsened as the pixel size becomes smaller. Consequently, the pixel signal is severely reduced, resulting in unacceptable signal to noise ratio (SNR).
Another issue that plagues image sensors is crosstalk. Crosstalk is a phenomenon by which a signal transmitted in one pixel or channel of a transmission system creates an undesired effect in another pixel or channel. For optical sensors, there are at least two types of crosstalk: (1) optical crosstalk, (2) electrical crosstalk. Optical crosstalk occurs when each pixel is not isolated optically. Since the light shielding metal layer only blocks the light that is incident from the perpendicular direction when light is incident in an angled direction or when light is reflected by the metal layers or the dielectric layer interface, scattered light in the pixel can easily travel to a neighboring pixel through the transparent dielectric layers. This effect is called a light piping effect. Optical crosstalk also occurs when the pixel size approaches the wavelength of the light. Diffraction causes a sharp increase in the amount of light that reaches adjacent photodiodes rather than the desired photodiode. Electrical crosstalk occurs when photo-generated electrons travel to adjacent pixels through the silicon substrate.
Accordingly, there is a strong need to circumvent these issues by introducing a new type of pixel architecture. Preferably, the new architecture needs to keep the CMOS compatibility for the easiness of the manufacture.
Recently, a nanoscale technology has emerged and opened up a new possibility of designing novel structures and combining materials in ways not possible in CMOS technology. It would therefore be advantageous to have a small pixel as well as the good optical fill factor, low optical crosstalk, and high QE employing the nanoscale technology, in particular, nanowires.